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dc.contributor.authorChaiken, Daviden_US
dc.contributor.authorAgarwal, Ananten_US
dc.date.accessioned2023-03-29T14:37:18Z
dc.date.available2023-03-29T14:37:18Z
dc.date.issued1993-10
dc.identifier.urihttps://hdl.handle.net/1721.1/149214
dc.description.abstractThis paper evaluates the tradeoffs involved when designing a directory-based protocol that implements coherent shared memory through a combination of hardware and software mechanisms. The fundamental design decisions involve balancing the size and cost of the hardware directory and control, the complexity of the software interface, and the overall performance of the system. In order to study these design problems, we experiment with a spectrum of cache-coherence schemes, raging from a full-map directory that supports all sharing patterns in hardware to an implementation that performs all memory-side actions in software.en_US
dc.relation.ispartofseriesMIT-LCS-TM-493
dc.titleSoftware-Extended Coherent Shared Memory: Performance and Costen_US


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