Space - Time Scheduling of Instruction-Level Parallelism on a Raw Machine
| dc.contributor.author | Lee, Walter | en_US |
| dc.contributor.author | Barua, R. | en_US |
| dc.contributor.author | Srikrishna, D. | en_US |
| dc.contributor.author | Babb, Jonathan | en_US |
| dc.contributor.author | Sarkar, V. | en_US |
| dc.contributor.author | Amarasinghe, Saman | en_US |
| dc.contributor.author | Agarwal, Anant | en_US |
| dc.date.accessioned | 2023-03-29T14:40:37Z | |
| dc.date.available | 2023-03-29T14:40:37Z | |
| dc.date.issued | 1997-12 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/149273 | |
| dc.description.abstract | Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocessors are ill-suited to exploit such advances. Achieving a high level of parallelism at a reasonable clock speed requires distributing the processor resources - a trend already visible in the dual-register-file architecture of the Alpha 21264. | en_US |
| dc.relation.ispartofseries | MIT-LCS-TM-572 | |
| dc.title | Space - Time Scheduling of Instruction-Level Parallelism on a Raw Machine | en_US |
